As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often sent to help recover the data. The clock signal determines when the data should be sampled or latched by a receiver circuit.
The clock signal may transition at the beginning of the time the data is valid. The receiver circuit, however, may require that the clock signal transition during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or “DLL,” may be used to regenerate a copy of the clock signal at a fixed phase shift with respect to the original clock signal.
FIG. 1 shows a section of a typical computer system component (100). Data (14) that is K bits wide is transmitted from circuit A (12) to circuit B (34) (also referred to as the “receiver circuit”). To aid in the recovery of the transmitted data, a clock signal (16) is also transmitted with the data (14). The circuits (12, 34) could also have a path to transmit data from circuit B (34) to circuit A (12) along with an additional clock signal (not shown). The clock signal (16) may transition from one state to another at the beginning of data transmission. Circuit B (34) requires a clock signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (16) may have degraded during transmission.
A DLL has the ability to regenerate the clock signal (16) to a valid state and to create a phase shifted version of the clock signal (16) to be used by other circuits. For example, the receiver circuit (34) may use the phase shifted version of the clock signal (16) as the receiver circuit's sampling signal. The receiver circuit's sampling signal determines when the input to the receiver circuit (34) should be sampled. The performance of a DLL is critical and must maintain a proper reference of time on the CPU, or generically, an integrated circuit.
FIG. 2 shows a block diagram of a typical DLL (200). Clock signal (201) is input to the DLL (200) to create a phased (i.e., delayed) output. Particularly, clock signal (201) is input to a voltage-controlled delay line (210) and to a phase detector (202) of the DLL (200). The phase detector (202) measures whether a phase difference between the clock signal (201) and an output signal, clk_out (217), of the voltage-controlled delay line (210) has a desired amount of delay. Depending on the phase difference, the phase detector (202) produces signals that control a charge pump (204). The phase detector (202) uses an UP signal (203) and DOWN signal (205) to adjust the charge pump (204) to increase or decrease its output current. To ensure that the charge pump (204) maintains some nominal current output, the charge pump (204) is internally biased. The internal biasing of the charge pump (204) is dependent on bias signals, VBP (209) and VBN (211), generated from a bias generator (208) (discussed below). The UP and DOWN signals (203, 205) adjust the current output of the charge pump (204) with respect to the nominal current set by the bias signals (209, 211).
The charge pump (204) adds or removes charge from a capacitor C1 (206), which, in turn, changes a voltage potential at the input of the bias-generator (208). The capacitor (206) is connected between a power supply, VDD, and a control signal, VCTRL (207). The bias-generator (208) produces the bias signals (209, 211) in response to the control signal (207), which, in turn, controls the delay of the voltage-controlled delay line (210) and, as mentioned above, maintains a nominal current output from the charge pump (204).
In FIG. 2, the voltage-controlled delay line (210) may be implemented using current starved elements. In other words, the delays of the voltage-controlled delay line (210) may be controlled by modifying the amount of current available for charging and discharging capacitances within the voltage-controlled, delay line (210). The linearity of a voltage controlled delay line's characteristics determines the stable range of frequencies over which the DLL (200) can operate. The output signal (217) of the voltage-controlled delay line (210) represents a phase delayed copy of clock signal (201) that is then used by other circuits.
Still referring to FIG. 2, the negative feedback created by the output signal (217) in the DLL (200) adjusts the delay through the voltage-controlled delay line (210). The phase detector (202) integrates the phase error that results between the clock signal (201) and the output signal (217). The voltage-controlled delay line (210) delays the output signal (217) by a fixed amount of time such that a desired delay between the clock signal (201) and the output signal (217) is maintained.
Accordingly, proper operation of the receiver circuit (34 in FIG. 1) depends on the DLL (200) maintaining a constant phase delay between the clock signal (201) and the output signal (217).